Low-current and high-speed phase-change memory devices and methods of driving the same

ABSTRACT

Phase-change memories in which phase is changed by varying the resistance by a small amount are provided. In the phase-change memory, a set state is defined as a state where amorphous nuclei are formed in a phase-change layer of a memory cell and the phase-change layer has an initial resistance that is higher than in a crystalline matrix, and a reset state is defined as a state where the number and/or the density of the amorphous nuclei are greater than those in the set state and a resistance is higher than in the set state. A current for writing the reset and set states is reduced to several hundred microamperes, and a period required for writing the reset and set states is reduced to several tens of nanoseconds to several hundred nanoseconds.

CLAIM OF PRIORITY

[0001] This application claims priority from Korean Patent ApplicationNo. 2003-21419, filed on Apr. 4, 2003, in the Korean IntellectualProperty Office, the contents of which are hereby incorporated byreference in their entirety as if set forth fully herein.

FIELD OF THE INVENTION

[0002] The present invention relates to phase-change memory usingresistance variation generated by, for example, changing a chalcogenidematerial into an amorphous/crystalline state.

BACKGROUND OF THE INVENTION

[0003] A phase-change memory is a device that operates using aphase-change layer formed of a chalcogenide material, which has anelectrical resistance that varies according to its phase. In the typicalphase-change memory, Joule heating is used as a heating source to causea change in phase. FIG. 1 shows a conventional phase-change memory cellarray.

[0004] As shown in FIG. 1, a conventional phase-change memory celltypically includes a cell transistor CTR having a gate connected to aword line WL as well as a phase-change memory cell PCC and a resistor Rthat are connected in series between a drain of the cell transistor CTRand a bit line BL. If a word line WL and a bit line BL are selected,current is applied to a selected phase-change memory cell PCCcorresponding to the selected word line WL and bit line BL to change thephase of the phase-change memory cell PCC.

[0005]FIG. 2A illustrates the principle of operation of the conventionalphase-change memory. Referring to FIG. 2A, a high current pulse of about2 mA to 3 mA is applied through a contact 10 to a phase-change layer 20for several microseconds to heat the phase-change layer 20 to a meltingtemperature T_(m). By rapidly cooling the phase-change layer 20immediately after interrupting the current pulse, a high-resistancewholly amorphous programming region 30 is formed at a contact portionbetween the phase-change layer 20 and the contact 10. In this case, thephase-change memory cell is in a “reset” state, which is defined as, forexample, storage of data “1.”

[0006] If a current pulse of about 1 mA to 2 mA is passed through thecontact 10 to the phase-change layer 20 for several microseconds andthen immediately cooled again, the wholly amorphous programming region30 crystallizes and the resistance of the phase-change layer 20decreases again. In this case, the phase-change memory cell is in a“set” state, which is defined as, for example, storage of data “0.”

[0007]FIG. 2B is a graph of resistance versus current for thephase-change memory cell of FIG. 2A. That is, current applied to thephase-change layer 20 is increased to about 0.4 mA to about 0.38 mA, anda variation in the resistance of the phase-change layer is measured.Referring to FIG. 2B, curve (a) represents the situation where thephase-change memory cell was initially in the reset state with a resetresistance R_(reset) of about 300 kΩ. When the current reached 1 mA to 2mA, the resistance markedly reduced to about 3 kΩ. Accordingly, thephase-change memory cell transited from the reset state to the set statein the current range of 1 mA to 2 mA. Thus, a set resistance R_(set) isabout 3 kΩ and a set current I_(set), which makes the transition to theset state, is about 1 mA to 2 mA. Curve (b) represents the case wherethe phase-change memory cell was initially in the set state with the setresistance R_(set). The resistance increases to about 300 kΩ when thecurrent increased from about 2 mA to 3 mA. Accordingly, the phase-changememory cell transited from the set state to the reset state. I_(reset)is about 2 mA to 3 mA.

[0008] To read stored data, a current, which is less than the currentI_(reset) and I_(set), is supplied or a voltage is applied to thephase-change memory cell and then a variation in resistance is detected.As shown in FIG. 2B, a switching ratio of the reset resistance to theset resistance may be 100 or more. In the conventional phase-changememory, application of a high current I_(reset) or I_(set) of severalmilliamperes is required for the transition to a wholly amorphous stateor a crystalline state, respectively, and data can be read or storedusing the larger variation in the resistance resulting from the phasetransition. In this case, the current required may be large enough tocause overheating in a cell transistor which may be a serious obstaclein producing highly integrated memory devices.

[0009] Also, for the conventional phase-change memory, it typicallytakes a period of about several microseconds to transit to the reset orset state, thereby slowing down the operating speed of the phase-changememory.

SUMMARY OF THE INVENTION

[0010] Embodiments of the present invention provide for establishing astate of a phase-change memory by writing a reset state as ahigh-resistance state by applying a reset current of about tenmicroamperes to several hundred microamperes to a phase-change layer ofa phase-change memory cell for a period of from about 10 nanoseconds toabout 100 nanoseconds and writing a set state as a low-resistance stateby applying a set current of about several tens of microamperes to thephase-change layer for a period of from about 10 nanoseconds to about100 nanoseconds. In certain embodiments of the present invention, theset current is from about 30 microamperes to about 50 microamperes, andthe reset current is from about 60 microamperes to about 200microamperes. A reset resistance of the phase-change layer may be fromabout 6 kΩ to about 20 kΩ. A ratio of reset resistance to set resistancemay be from about 1.5 to about 3.

[0011] In further embodiments of the present invention, each of a risingtime and a falling time of the reset current or the set current is fromabout 1 nanosecond to about 4 nanoseconds. The current applied to thephase-change layer for reading the reset and/or the set states may befrom about 3 μA to about 6 μA and the time required for reading thereset and/or the set states may be from about 5 nanoseconds to about 10nanoseconds.

[0012] In additional embodiments of the present invention, aphase-change memory, is driven by writing a set state by applying a setcurrent of from about 30 μA to about 50 μA to a crystalline phase-changelayer of a memory cell and writing a reset state by applying a resetcurrent of from about 60 μA to about 200 μA to the phase-change layer.The reset state is defined as a state where a resistance of thephase-change layer is greater than in the set. A ratio of resetresistance to set resistance of the phase-change layer may be from about1.5 to about 3. The current for reading the reset state and/or the setstate may be from about 3 μA to about 6 μA, and a period required forreading the reset state and/or the set state may be from about 5nanoseconds to about 10 nanoseconds. A time required for writing thereset state and/or the set state may be from about 10 nanoseconds toabout 100 nanoseconds. A reset resistance of the phase-change layer maybe from about 6 kΩ to about 20 kΩ and a set resistance of thephase-change layer may be from about 4 kΩ to about 6 kΩ.

[0013] In yet other embodiments of the present invention, a phase-changememory includes a first electrode contact, a phase-change layer on thefirst electrode contact and a second electrode contact on thephase-change layer. A set state is a state in which amorphous nuclei areformed in the phase-change layer that has a set resistance of from about4 kΩ to 6 kΩ, and a reset state is a state in which the number anddensity of the amorphous nuclei are greater than in the set state andhas a reset resistance of about 6 kΩ to 20 kΩ. The current for writingthe reset state and/or the set state on the phase-change layer may befrom about 10 μA to about 200 μA, and a period required for writing thereset state and/or the set state from the phase-change layer may be fromabout 10 nanoseconds to about 100 nanoseconds. In particularembodiments, the current for writing the set state in the phase-changelayer may be from about 30 μA to about 50 μA, and the current forwriting the reset state in the phase-change layer is from about 60 μA toabout 200 μA. The diameter of the first electrode contact to which thecurrent is applied to write the reset and set states in the phase-changelayer may be from about 40 nanometers to about 70 nanometers.

[0014] In particular embodiments of the present invention, the risingtime and falling time for writing the reset state and/or the set statein the phase-change layer is from about 1 nanosecond to about 4nanoseconds. The current for reading the reset state and/or the setstate may be from about 3 μA to about 6 μA, and a time required forreading the reset state and/or the set state is from about 5 nanosecondsto about 10 nanoseconds.

[0015] In still further embodiments of the present invention, aphase-changeable memory device includes a phase change memory cell and asense amplifier circuit configured to detect a change in resistance ofthe phase change memory cell from a first resistance associated with afirst state of the phase change memory cell to a second resistanceassociated with a second state of the phase change memory cell, thesecond resistance being from about 1.5 to about 3 times the firstresistance. For example, the first resistance may be from about 4 kΩ toabout 6 kΩ and the second resistance may be from about 6 kΩ to about 20kΩ.

[0016] The phase-changeable memory device may also include a set currentsource configured to provide a set write current of from about 30 μA toabout 50 μA to the phase change memory cell. The set write current maybe provided to the phase-change memory cell for from about 10nanoseconds to about 100 nanoseconds. The phase-changeable memory devicemay also include a reset current source configured to provide a resetwrite current of from about 60 μA to about 200 μA to the phase changememory cell. The reset write current may be provided to the phase-changememory cell for from about 10 nanoseconds to about 100 nanoseconds.

[0017] In yet other embodiments of the present invention, a phase changememory includes first and second electrode contacts and a phase-changelayer between the first and second electrode contacts. The phase changelayer provides a first state established by a first number of amorphousnuclei in a crystalline matrix in a region adjacent an interface betweenthe phase-change layer and the first electrode. The phase change layermay also provide a second state established by a second number ofamorphous nuclei in a crystalline matrix in the region adjacent theinterface between the phase-change layer and the first electrode, thesecond number being greater than the first number. The first number ofamorphous nuclei and the second number of amorphous nuclei may provide aratio of resistances of the phase-change layer of from about 1.5 toabout 3. The first state of the phase-change layer may provide aresistance of the phase-change layer of from about 4 kΩ to about 6 kΩand the second state the phase-change layer may provide a resistance ofthe phase-change layer of from about 6 kΩ to about 20 kΩ.

[0018] In particular embodiments of the present invention, the currentfor writing the first state or the second state on the phase-changelayer is from about 10 μA to about 200 μA, and the period required forwriting the first state or the second state from the phase-change layeris from about 10 nanoseconds to about 100 nanoseconds. For example, thecurrent required for writing the first state in the phase-change layermay be from about 30 μA to about 50 μA, and the current required forwriting the second state in the phase-change layer may be from about 60μA to about 200 μA. The diameter of the first electrode contact to whicha current is applied to write the first and second states in thephase-change layer may be from about 40 nanometers to about 70nanometers. The current for reading the first state and/or the secondstate may be from about 3 μA to about 6 μA, and a time required forreading the first state and/or the second state may be from about 5nanoseconds to about 10 nanoseconds.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a diagram of a conventional phase-change memory cellarray;

[0020]FIG. 2A is a diagram illustrating the reset and set principles ofthe conventional phase-change memory;

[0021]FIG. 2B is a graph of resistance versus programming current of thephase-change memory cell of FIG. 2A;

[0022]FIG. 3 is a diagram illustrating the reset and set principles of aphase-change memory according to some embodiments of the presentinvention;

[0023]FIGS. 4A and 4B are diagrams showing comparisons between phasetransitions of the phase-change memory of FIG. 2 and the phase-changememory of FIG. 3;

[0024]FIG. 5A is a circuit diagram of certain embodiments of thephase-change memory of FIG. 3;

[0025]FIG. 5B is a sectional view of certain embodiments of thephase-change memory of FIG. 3;

[0026]FIG. 6A is a graph illustrating I-V characteristics of theconventional phase-change memory after being in the reset state;

[0027]FIG. 6B is a graph illustrating I-V characteristics of thephase-change memory according to embodiments of the present inventionafter being in the reset state;

[0028]FIG. 7 is a graph of the resistance of a phase-change layer withrespect to the programming current in the phase-change memory accordingto embodiments of the present invention;

[0029]FIG. 8 is a diagram showing applications of current pulses forreading, reset, and set in the phase-change memory according toembodiments of the present invention;

[0030]FIG. 9 is a graph showing the resistance of the phase-change layerafter repetition of reset and set in the phase-change memory accordingto embodiments of the present invention;

[0031]FIG. 10 is a graph showing the resistance of the phase-changelayer after alternate repetition of reset and set in the phase-changememory according to embodiments of the present invention; and

[0032]FIG. 11 is a graph that compares the activation energies E_(a) forthe set state of the conventional phase-change memory and thephase-change memory according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0033] The present invention will now be described more fully withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied indifferent forms and should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the size or thickness of layers and regions are exaggeratedfor clarity. Like numbers refer to like elements. As used herein theterm “and/or” includes any and all combinations of one or more of theassociated listed items.

[0034] It will be understood that although the terms first and secondmay be used herein to describe various regions, layers, and/or sections,these regions, layers, and/or sections should not be limited by theseterms. These terms are only used to distinguish one region, layer, orsection from another region, layer, or section. Thus, a first region,layer, or section discussed below could be termed a second region,layer, or section, and similarly, a second region, layer or sectioncould be termed a first region, layer or section without departing fromthe teachings of the present invention.

[0035] Embodiments of the present invention are described herein withreference to a particular theory of operation. However, the presentinvention is not limited to a particular theory of operation, which isprovided for purposes of clarity and not limitation.

[0036]FIG. 3 is a diagram illustrating the set/reset principles of aphase-change memory according to embodiments of the present invention. Alow current pulse of several tens to several hundred microamperes, forexample, from about 60 μA to about 200 μA, is supplied through a contact110 to a crystalline phase-change layer 120 for a short amount of time,for example, from about 10 ns to about 100 ns, so as to locally heat thephase-change layer 120 to a melting temperature T_(m). Then, by rapidlycooling the phase-change layer 120 immediately after the current pulseis interrupted, amorphous nuclei 132 a are formed locally at a contactportion between the phase-change layer 120 and the contact 110, therebyforming a programming region 130, which has a resistance higher than aninitial resistance R_(i) of the crystalline phase-change layer 120. Thephase-change memory cell is in a “reset” state, which may be defined asa storage of data “1.” That is, the reset state in the phase-changememory of embodiments of the present invention differs from a whollyamorphous state in the conventional phase-change memory, because in thereset state of the phase-change memory of embodiments of the presentinvention, amorphous nuclei are distributed in a crystalline matrix. Fora contact 110 with a predetermined diameter and initial resistance, thereset resistance R_(reset) depends on a reset current I_(reset) andperiod over which the reset current I_(reset) is applied. For example,when the diameter of the contact 110 is about 60 nm and the initialresistance ranges from 4 kΩ to 6 kΩ, then, if a current pulse in therange of several tens of microamperes to several hundred microampereswith a period of several tens of nanoseconds is supplied through thecontact 110, the reset resistance R_(reset) ranges from about 6 kΩ to 20kΩ.

[0037] If the phase-change layer 120 is held at a crystallizationtemperature for a relatively short amount of time of about 10nanoseconds to 100 nanoseconds, in particular embodiments of the presentinvention, about 50 nanoseconds to about 100 nanoseconds, by applying alow current pulse of several tens of microamperes, in particularembodiments of the present invention, about 30 μA to about 50 μA, (i.e.,a set current I_(set)) to the phase-change layer 120 and then cooledagain, the amorphous nuclei 132 a become smaller to form amorphousnuclei 132 b, which are smaller and fewer in number than the amorphousnuclei 132 a. Thus, a phase-change region 140 with a reduced density ofthe amorphous nuclei 132 b is formed. The phase-change memory cell is ina “set” state, which is defined as a storage of data “0.” As the densityand number of high-resistance amorphous nuclei decrease, a setresistance R_(set) is reduced to from about 4 kΩ to about 6 μA, which islower than the reset resistance R_(reset).

[0038] As described above, when the phase-change memory cell transitsfrom the reset state to the set state, a low programming region 140 withthe reduced number and/or density of amorphous nuclei is formed. It hasbeen confirmed by experimental results that, although a ratio of thereset resistance R_(reset) to the set resistance R_(set) ranging from1.5 to 3 is much less than a ratio of several hundred in theconventional memory, the set and reset resistance change can besufficiently sensed. In certain embodiments of the present invention, toobtain the ratio of the reset resistance R_(reset) to the set resistanceR_(set) ranging from about 1.5 to about 3, a set current I_(set) ofseveral tens of microamperes to several hundred microamperes is appliedfor a period of several tens of nanoseconds.

[0039] To read stored data, a current of less than the set and resetcurrents I_(set) or I_(reset), for example, a current of about 3 μA to 6μA is supplied through the contact 110 and a resistance is measured,which is compared with the set and reset resistances R_(set) andR_(reset). The time required for determining the state of thephase-change memory cell ranges from about 5 nanoseconds to 10nanoseconds.

[0040] In certain embodiments of the present invention, amorphous nucleiare formed using set and reset currents I_(set) and I_(reset) of severaltens of microamperes, which are less than the set and reset currentsused in the conventional phase-change memory and produces a ratio of thereset resistance R_(reset) to the set resistance R_(set) of about 1.5 to3, through which the phase-change memory can perform data writing anddata reading. Since the writing current and pulse duration are less thanthose in the conventional memory, a low-current and high-speedphase-change memory may be provided.

[0041]FIGS. 4A and 4B are diagrams showing comparisons between phasetransitions of the phase-change memory of FIG. 2 and the phase-changememory of FIG. 3. Referring to FIG. 4A, a conventional phase-changememory (a) as described with reference to FIG. 2 provides a set andreset resistance by transiting from a wholly crystalline state 20 to awholly amorphous state 30 and vice versa. Thus, there is a largevariation in the resistance when changing states in the conventionalphase-change memory cell. On the other hand, the phase-change memory (b)of embodiments of the present invention provides a set and resetresistance by transiting the state of the phase-changeable material froma first state with a first amount of amorphous nuclei in a crystallinematrix 130 to the state with fewer amorphous nuclei 140. Accordingly,there is a relatively small variation in the resistance when changingstates in the phase-change memory cell according to embodiments of thepresent invention compared with the conventional phase-change memory(a).

[0042] Referring to FIG. 4B, the conventional phase-change memory (a)covers far wider ranges of current I and voltage V than the phase-changememory (b). In the conventional phase-change memory (a), to form awholly amorphous region, it typically takes a longer time to generateand grow amorphous nuclei in a liquid state. Likewise, to crystallizethe wholly amorphous region, it typically takes more than about 100nanoseconds to generate and grow crystalline nuclei in the amorphousregion. However, in the phase-change memory (b) of embodiments of thepresent invention, while amorphous nuclei are formed in the reset state,the number and volume of the amorphous nuclei are reduced in the setstate. Therefore, narrower ranges of current I and voltage V are used inthe phase-change memory (b) of embodiments of the present invention thanin the conventional phase-change memory. Forming a region whereamorphous nuclei are distributed typically requires only low current anda short duration current pulse in order to generate amorphous nuclei ina liquid state. That is, nucleation dominates growth of nuclei in thecontact portion. Also, since there exists a crystalline matrix in theregion where the amorphous nuclei are distributed, when transiting froma reset state to a set state, the already existing crystalline matrixwill grow without the need of nucleation. That is, the expansion of thecrystalline matrix dominates nucleation of the crystalline matrix.Therefore, the region where the amorphous nuclei are distributed can beeasily transformed to a region where the number and volume of theamorphous nuclei are reduced, even with a small current and over a shortperiod of time. Thus, phase-change memories according to embodiments ofthe present invention may exhibit low-current and high-speedcharacteristics.

[0043] The following Table 1 shows the characteristics of theconventional phase-change memory and the phase-change memory of certainembodiments of the present invention. TABLE 1 Comparison of Phase ChangeMemory Characteristics Condition of Condition of Set Reset set resetR_(reset)/R_(sct) Conventional Wholly Wholly 2 to 3 1 to 2 100 memorycrystalline amorphous milliamperes milliamperes or state state or higherfor several higher several for several microseconds microseconds TheState where Number and several tens several tens 1.5 to 3 presentamorphous size of to several of invention nuclei are amorphous hundredmicroamperes formed nuclei are microamperes for 10 to 100 larger thanfor 10 to 100 nanoseconds in set state nanoseconds

[0044]FIG. 5A is a circuit diagram of the phase-change memory accordingto certain embodiments of the present invention, and FIG. 5B is asectional view of the phase-change memory according to certainembodiments of the present invention, which can be manufactured by a0.24-μm CMOS process.

[0045] Referring to FIG. 5A, phase-change memory according to certainembodiments of the present invention operates by a twin-cell switchingmethod excluding a reference cell and includes a set state cell and areset state cell. The phase-change memory further includes two currentsources I_(reset) and I_(set) and a current sense amplifier S/A fordetecting a difference in resistance between the two cells. A memorycell includes a single cell transistor CTR, in which a gate is connectedto a word line WLi or WLj, a phase-change memory cell PCC and a resistorR, which are connected series with each other between a drain of thecell transistor CTR and a bit line BL.

[0046] Referring to FIG. 5B, a phase-change layer 200 is disposedbetween a first metal interconnection 210, which is connected to asource S of a MOS transistor 260 formed on a substrate 250 through aconductive plug 270, and a second metal interconnection 220, and isconnected to the metal interconnections 210 and 220 through a lowerelectrode contact 230 and an upper electrode contact 240, respectively.The phase-change layer 200 may be formed of a binary compound such asGaSb, InSb, InSe, Sb₂Te₂, and/or GeTe, a ternary compound such asGe₂Sb₂Te₅, InSbTe, GaSeTe, SnSb₂Te₄, and/or InSbGe, and/or a quaternarycompound such as AgIbSbTe, (Ge, Sn)SbTe, and/or GeSb(SeTe).

[0047] Spacers 245 are formed to reduce a contact area between thephase-change layer 200 and the lower electrode contact 230. The lowerelectrode contact 230 may include a Ti/TiN plug, which is formed bydepositing Ti/TiN in a lower electrode contact hole by chemical vapordeposition (CVD) and planarizing the Ti/TiN by chemical mechanicalpolishing (CMP). The thickness of the spacers 245 may be controlled suchthat a diameter of the contact is about 40 nanometers to about 70nanometers, and in certain embodiments, about 60 nanometers. A Ti/TINlayer 205 may be formed on the phase-change layer 200 that is formed of,for example, Ge₂Sb₂Te₅, thereby reinforcing adhesion between thephase-change layer 200 and the upper electrode contact 240. The upperelectrode contact 240 includes a W plug, which is formed by depositing Win an upper electrode contact hole by CVD and planarizing the W by CMP.A drain line is formed to include the first metal interconnection 210connected to a drain D of the MOS transistor 260 through the conductiveplug 270. The MOS transistor 260 can be formed by the 0.24-μm CMOSprocess. For example, a 35 Å thick gate insulating layer can be formedso that a current of 2 milliamperes or more can be applied at a gatevoltage of 3 V. Also, a silicide process may be further performed on thesource S/drain D in order to reduce the series resistance between thesource S/the drain D and the conductive plug 270. As a result, theseries resistance may be less than about 10 Ω.

[0048] A current flows from the lower electrode contact 230 through thephase change layer 200 to the upper electrode contact 240. A change inphase occurs at an interface between the phase-change layer 200 and thelower electrode contact 230 due to Joule heating and rapid coolingresulting from the interruption of the current.

[0049] The invention will now be described in more detail in thefollowing non-limiting examples.

[0050] The invention will now be described in more detail in thefollowing non-limiting examples. In particular, the suitability of thephase-change memory of the present invention for an actual device wasdemonstrated through reset/set transition, resistance ratio, and achange in I-V curve.

EXAMPLE 1

[0051]FIG. 6A is a graph illustrating I-V characteristics of theconventional phase-change memory after being in the reset state. When avoltage greater than a threshold voltage V_(th) was applied to thedevice in the reset state (“1” state), the device was electronicallyswitched to a low-resistance dynamic state, thereby allowing low-voltageprogramming. The threshold voltage V_(th) was 1.0 V or higher and aprogramming current for writing set/reset was 1.0 milliampere or higher.

[0052]FIG. 6B is a graph illustrating I-V characteristics of thephase-change memory according to certain embodiments of the presentinvention after being in the reset state as a result of the applicationof a current pulse of 100 μA with a period of 50 nanoseconds. Thethreshold voltage V_(th), was 200 mV, which is lower than in theconventional memory due to locally small amorphous nucleation. Also, aprogramming current for writing set/reset was markedly reduced to about40 μA, which is less than in the conventional memory.

EXAMPLE 2

[0053] The ranges of the reset and set currents I_(reset) and I_(set)can be determined by varying the resistance of the phase-change layer120 by increasing the current. FIG. 7 is a graph of the resistance ofthe phase-change layer 120 with respect to the programming current inthe phase-change memory according to certain embodiments of the presentinvention.

[0054] Initially, (a) started from the reset state (where an initialresistance was about 10.86 kΩ) by applying a current of 100 μA for aperiod of about 50 nanoseconds. In the current range of 30 μA to 50 μA,the resistance markedly decreased to 4 kΩ or lower. Thus, thephase-change memory cell transited from the reset state to the set statein the current range of 30 μA to 50 μA. That is, the set current I_(set)can be selected in the range of 30 μA to 50 μA.

[0055] Also, (b) represents a phase-change memory cell which wasinitially in the set state (where the resistance was slightly higherthan 4 kΩ). As the current increased above 60 μA, the resistanceincreased. When the current reached about 100 μA, the resistance wassaturated. Accordingly, the phase-change memory cell transited from theset state to the reset state when the current was about 60 μA or higher,and a stable reset current I_(reset) of about 100 μA can be selected.

EXAMPLE 3

[0056]FIG. 8 is a diagram showing applications of current pulses forreading, reset, and set in the phase-change memory according to certainembodiments of the present invention. Current I_(reading) for readingthe writing state of the phase-change memory cell can be taken within arange that does not affect R_(reset) and R_(set). Also, a rising timeand falling time should be considered when applying the reading currentI_(reading) and interrupting the current. It can be expected that arising time and a falling time typically range from 1 nanoseconds to 4nanoseconds each.

[0057] An experiment was performed in which the rising time and fallingtime for set were 4 nanoseconds each and the rising time and fallingtime for reset and read were 2 nanoseconds each. A writing current and apulse width were applied in the range of 100 μA/100 nanoseconds forreset/set. Specifically, 100 μA/50 nanoseconds was applied for reset and40 μA/100 nanoseconds was applied for set. A reading current and a pulsewidth were applied in the range of 6 μA/10 nanoseconds in order tominimize effects during reading.

[0058] When reading, reset, and set were repeated under the aboveconditions, the initial resistance was 4 kΩ, R_(reset) was 12 kΩ, andR_(set) was 5 kΩ. Thus, the phase-change memory of certain embodimentsof the present invention allows writing and reading under the aboveconditions.

EXAMPLE 4

[0059]FIG. 9 is a graph showing the resistance of the phase-change layer120 after repetition of reset and set in the phase-change memoryaccording to the present invention. That is, the phase-change memorycell was repeatedly reset, i.e., data “1” was repeatedly written andread, and the phase-change memory cell was repeatedly set, i.e., data“0” was repeatedly written and read. The reset was under conditions of100 μA/50 nanoseconds, the set was under conditions of 40 μA/100nanoseconds, and the reading was performed under conditions of 6 μA/10nanoseconds. From the results, it can be seen that the reset and setresistances R_(reset) and R_(set) remained substantially constant, whichis a requirement for the proper functions of a memory.

EXAMPLE 5

[0060]FIG. 10 is a graph showing the resistance of the phase-changelayer 120 after alternate repetition of reset and set in thephase-change memory according to certain embodiments of the presentinvention. From the results, it can be seen that a ratio of the resetresistance R_(reset) to the set resistance R_(set) was substantiallyconstant.

EXAMPLE 6

[0061]FIG. 11 is a graph that compares the activation energies E_(a) forthe set state of the conventional phase-change memory and thephase-change memory according to certain embodiments of the presentinvention, which provides different driving methods of the phase-changememory. For the set operation, while an activation energy E_(a) of about2.25 eV was required in the conventional memory, activation energiesE_(a) of about 0.70 eV, 0.74 eV, and 0.78 eV were required in theembodiments of present invention illustrated in FIG. 1I.

[0062] A conventional set operation defines reset as a high-resistancestate. Thus, transition from the reset state to the set state, i.e., acrystalline state needs a high activation energy for nucleation andgrowth of crystalline nuclei. However, a set operation of certainembodiments of the present invention defines reset as a relativelylow-resistance state. Thus, the transition from the reset state to theset state only requires the growth of a crystalline matrix includingamorphous nuclei, and the activation energy is much lower than in theconventional memory.

[0063] The phase-change memory according to certain embodiments of thepresent invention may be characterized by particular physical and/orperformance characteristics. In particular, when the diameter of acontact portion between a phase-change layer and a lower electrodecontact ranges within several tens of nanometers, the phase-changememory exhibits suitable characteristics with respect to initialresistance range and/or dynamic resistance range. A reset resistanceranges from 6 kΩ to 20 kΩ, and a set resistance ranges from 4 kΩ to 6kΩ. Thus, data sensing is enabled in a ratio of reset resistance to setresistance ranging from about 1.5 to about 3.

[0064] According to embodiments of the present invention, the phase of acrystalline phase-change layer can be changed by programming in a regionwhere resistance varies within a very small range, and set and resetstates are defined based on this phase-change method. Thus, the currentrequired for reset can be reduced to several microamperes to severalhundred microamperes, and with a reduced volume of amorphous nuclei, thetime required to transit to the set state by crystallization isshortened. Also, the current required to transit to the set state isreduced to several microamperes to several hundred microamperes.Therefore, the phase-change memory of certain embodiments of the presentinvention can have high-speed and low-current characteristics, therebyallowing formation of highly integrated devices.

[0065] While embodiments of the present invention have been describedprimarily with reference to two states where each state includesamorphous nuclei in a crystalline matrix, embodiments of the presentinvention should not be limited to such devices. Thus, for example,embodiments of the present invention may include devices where one stateis wholly crystalline or wholly amorphous in the region of the contact.Also, more that two states may be provided having amorphous nuclei in acrystalline matrix. The number of such states may only be limited by theability to control the transition of the phase-changeable material andthe ability to sense resulting changes in resistance.

[0066] While the present invention has been particularly shown anddescribed with reference to particular embodiments thereof, it will beunderstood by those of ordinary skill in the art that various changes inform and details may be made therein without departing from the spiritand scope of the present invention as defined by the following claims.

What is claimed is:
 1. A method of establishing a state of aphase-change memory, comprising: writing a reset state as ahigh-resistance state by applying a reset current of about tenmicroamperes to several hundred microamperes to a phase-change layer ofa phase-change memory cell for a period of from about 10 nanoseconds toabout 100 nanoseconds; and writing a set state as a low-resistance stateby applying a set current of less than about several tens ofmicroamperes to the phase-change layer for a period of from about 10nanoseconds to about 100 nanoseconds.
 2. The method of claim 1, whereinthe set current is from about 30 microamperes to about 50 microamperes,and the reset current is from about 60 microamperes to about 200microamperes.
 3. The method of claim 1, wherein a reset resistance ofthe phase-change layer is from about 6 kΩ to about 20 kΩ.
 4. The methodof claim 1, wherein the phase-change memory has a ratio of resetresistance to set resistance of from about 1.5 to about
 3. 5. The methodof claim 1, wherein each of a rising time and a falling time of thereset current or the set current is from about 1 nanosecond to about 4nanoseconds.
 6. The method of claim 1, wherein a current applied to thephase-change layer for reading the reset and/or the set states is fromabout 3 μA to about 6 μA and a time required for reading the resetand/or the set states is from about 5 nanoseconds to about 10nanoseconds.
 7. A method of driving a phase-change memory, the methodcomprising: writing a set state by applying a set current of from about30 μA to about 50 μA to a crystalline phase-change layer of a memorycell; and writing a reset state by applying a reset current of fromabout 60 μA to about 200 μA to the phase-change layer, wherein the resetstate is defined as a state where a resistance of the phase-change layeris greater than in the set.
 8. The method of claim 7, wherein a ratio ofreset resistance to set resistance of the phase-change layer is fromabout 1.5 to about
 3. 9. The method of claim 7, wherein a current forreading the reset state and/or the set state is from about 3 μA to about6 μA, and a period required for reading the reset state and/or the setstate is from about 5 nanoseconds to about 10 nanoseconds.
 10. Themethod of claim 7, wherein a time required for writing the reset stateand/or the set state is from about 10 nanoseconds to about 100nanoseconds.
 11. The method of claim 7, wherein a reset resistance ofthe phase-change layer is from about 6 kΩ to about 20 kΩ.
 12. The methodof claim 7, wherein a set resistance of the phase-change layer is fromabout 4 kΩ to about 6 kΩ.
 13. A phase-change memory comprising: a firstelectrode contact; a phase-change layer on the first electrode contact;and a second electrode contact on the phase-change layer, wherein a setstate is a state in which amorphous nuclei are formed in thephase-change layer that has a set resistance of from about 4 kΩ to 6 kΩ,and a reset state is a state in which the number and density of theamorphous nuclei are greater than in the set state and has a resetresistance of about 6 kΩ to 20 kΩ.
 14. The memory of claim 13, wherein acurrent for writing the reset state and/or the set state on thephase-change layer is from about 10 μA to about 200 μA, and a periodrequired for writing the reset state and/or the set state from thephase-change layer is from about 10 nanoseconds to about 100nanoseconds.
 15. The memory of claim 13, wherein a current for writingthe set state in the phase-change layer is from about 30 μA to about 50μA, and a current for writing the reset state in the phase-change layeris from about 60 μA to about 200 μA.
 16. The memory of claim 13, whereina diameter of the first electrode contact to which the current isapplied to write the reset and set states in the phase-change layer isfrom about 40 nanometers to about 70 nanometers.
 17. The memory of claim13, wherein a rising time and a falling time for writing the reset stateand/or the set state in the phase-change layer is from about 1nanosecond to about 4 nanoseconds.
 18. The memory of claim 13, wherein acurrent for reading the reset state and/or the set state is from about 3μA to about 6 μA, and a time required for reading the reset state and/orthe set state is from about 5 nanoseconds to about 10 nanoseconds. 19.The memory of claim 14, wherein a current for reading the reset stateand/or the set state iss from about 3 μA to about 6 μA, and a timerequired for reading the reset state and/or the set state is from 5nanoseconds to about 10 nanoseconds.
 20. A phase-changeable memorydevice, comprising: a phase change memory cell; and a sense amplifiercircuit configured to detect a change in resistance of the phase changememory cell from a first resistance associated with a first state of thephase change memory cell to a second resistance associate with a secondstate of the phase change memory cell, the second resistance being fromabout 1.5 to about 3 times the first resistance.
 21. Thephase-changeable memory device of claim 20, wherein the first resistanceis from about 4 kΩ to about 6 kΩ and the second resistance is from about6 kΩ to about 20 kΩ.
 22. The phase-changeable memory device of claim 20,further comprising a set current source configured to provide a setwrite current of from about 30 μA to about 50 μA to the phase changememory cell.
 23. The phase-changeable memory device of claim 22, whereinthe set write current is provided to the phase-change memory cell forfrom about 10 nanoseconds to about 100 nanoseconds.
 24. Thephase-changeable memory device of claim 22, further comprising a resetcurrent source configured to provide a reset write current of from about60 μA to about 200 μA to the phase change memory cell.
 25. Thephase-changeable memory device of claim 24, wherein the reset writecurrent is provided to the phase-change memory cell for from about 10nanoseconds to about 100 nanoseconds.
 26. A phase change memory,comprising: first and second electrode contacts; a phase-change layerbetween the first and second electrode contacts, the phase change layerproviding a first state established by a first number of amorphousnuclei in a crystalline matrix in a region adjacent an interface betweenthe phase-change layer and the first electrode.
 27. The phase changememory of claim 26, wherein the phase change layer further provides asecond state established by a second number of amorphous nuclei in acrystalline matrix in the region adjacent the interface between thephase-change layer and the first electrode, the second number beinggreater than the first number.
 28. The phase change memory of claim 27,wherein the first number of amorphous nuclei and the second number ofamorphous nuclei provide a ratio of resistances of the phase-changelayer of from about 1.5 to about
 3. 29. The phase change memory cell ofclaim 27, wherein the first state of the phase-change layer provides aresistance of the phase-change layer of from about 4 to about 6 kΩ andthe second state the phase-change layer provides a resistance of thephase-change layer of from about 6 to about 20 kΩ.
 30. The phase changememory cell of claim 27, wherein a current for writing the first stateor the second state on the phase-change layer is from about 10 μA toabout 200 μA, and a period required for writing the first state or thesecond state from the phase-change layer is from about 10 nanoseconds toabout 100 nanoseconds.
 31. The phase change memory cell of claim 27,wherein a current required for writing the first state in thephase-change layer is from about 30 μA to about 50 μA, and a currentrequired for writing the second state in the phase-change layer is fromabout 60 μA to about 200 μA.
 32. The phase change memory cell of claim27, wherein a diameter of the first electrode contact to which a currentis applied to write the first and second states in the phase-changelayer is from about 40 nanometers to about 70 nanometers.
 33. The phasechange memory cell of claim 27, wherein a current for reading the firststate and/or the second state is from about 3 μA to about 6 μA, and atime required for reading the first state and/or the second state isfrom about 5 nanoseconds to about 10 nanoseconds.
 34. A method ofoperating a phase change memory, comprising: establishing logic statesin a phase change memory by controlling amorphous nucleation in acrystalline matrix of a phase-changeable material.
 35. The method ofclaim 34, wherein a first logic state is established by a first numberof amorphous nuclei in the crystalline matrix and a second logic stateis established by a second number of amorphous nuclei in the crystallinematrix in the, the second number being greater than the first number.36. The method of claim 35, wherein the first number of amorphous nucleiand the second number of amorphous nuclei provide a ratio of resistancesof the phase-changeable material of from about 1.5 to about
 3. 37. Themethod of claim 35, wherein the first logic state provides a resistanceof the phase-change layer of from about 4 kΩ to about 6 kΩ and thesecond logic state provides a resistance of the phase-change layer offrom about 6 kΩ to about 20 kΩ.
 38. The method of claim 35, whereincontrolling amorphous nucleation comprises controlling a current forwriting the first logic state or the second logic state to be from about10 μA to about 200 μA, and a period required for writing the first logicstate or the second logic state to be from about 10 nanoseconds to about100 nanoseconds.
 39. The method of claim 35, wherein controllingamorphous nucleation comprises: controlling a current for writing thefirst logic state to be from about 30 μA to about 50 μA; and controllinga current or writing the second logic state to be from about 60 μA toabout 200 μA.
 40. The method of claim 35, wherein a diameter of thefirst electrode contact to which a current is applied to write the firstand second logic states is from about 40 nanometers to about 70nanometers.
 41. The method of claim 35, further comprising controlling acurrent for reading the first logic state and/or the second logic stateto be from about 3 μA to about 6 μA, and a time for reading the firststate and/or the second state to be from about 5 nanoseconds to about 10nanoseconds.